1. Field of the Invention
The present invention generally relates to PCI-X (Peripheral Component Interconnect-X) bridges, and more particularly to Host/PCI-X bridges.
2. Description of the Related Art
In a conventional computer system, a Host/PCI-X bridge couples a Front Side Bus (FSB) and a PCI-X Bus (called PCI-X Bus 0). There may be a PCI-X device coupled to the PCI-X Bus 0. The FSB is connected to at least a processor and main memory. The processor, the main memory and the PCI-X device communicate with each other via the FSB, the Host/PCI-X bridge, and the PCI-X Bus 0.
The communication between the main memory and the PCI-X device can be a split transaction. A split transaction consists of a request by a requester followed by a completion by a completer at a later time. Assume the PCI-X device needs to read data from main memory. As a requester, the PCI-X device sends a read request to the Host/PCI-X bridge via the PCI-X bus 0. The read request is called a split read request. The Host/PCI-X bridge responds by sending back a split read response to the PCI-X device informing the PCI-X device that split completion data will be sent to it at a later time. The Host/PCI-X bridge then reinitiates the split read request to the main memory via the FSB. When the bridge has gathered all the requested data (called split completion data) from the main memory via the FSB, the bridge sends the split completion data to the PCI-X device via the PCI-X bus 0.
The mechanism used by the Host/PCI-X bridge to deliver the split completion data to the PCI-X device on the PCI-X Bus 0 has a large impact on the efficiency and latency of the computer system. Latency is defined as the time period from the time a data item is sent from a source to the time the data item is received at a destination. Efficiency of a system can be defined as how well the system's resources are used. A system operating with high efficiency means that a high percentage of the system's resources are used for the ultimate purposes of those resources, and without unnecessary overhead. For example, in the case of a bus, the system operates with high efficiency if a high percentage of the bus bandwidth is used for transferring data (which is the ultimate purpose of a bus). If a large percentage of the bus bandwidth is not used for transferring data (for instance, the bus is idle), the system operates with low efficiency. However, efficiency and latency are two competing goals in conventional computer systems.
In some PCI-X systems, low latency is the main concern. However, low latency typically causes low efficiency. In such systems, the Host/PCI-X bridge is designed to start sending split completion data to the PCI-X device as soon as it receives an entire first packet of 128 bytes (the minimum amount of data allowed transferred in a block transfer in a PCI-X system) of split completion data from the main memory. As a result, these systems operate with low latency. However, when the Host/PCI-X bridge approaches the last byte of the first packet of 128 bytes, if the Host/PCI-X bridge has not received an entire second packet of 128 bytes of split completion data from the main memory, the Host/PCI-X bridge stops after the last byte of the first packet. When the Host/PCI-X bridge has received the entire second packet of 128 bytes, the Host/PCI-X bridge sends the second packet of 128 bytes to the PCI-X device via the PCI-X bus 0, and so on. As a result, bus usage of the PCI-X bus 0 is not efficient because the PCI-X bus 0 may be idle (i.e., no device is using the bus) between the packets which the Host/PCI-X bridge forwards from the main memory to the PCI-X device.
In some other PCI-X systems, efficiency is the main concern. However, high efficiency typically causes high latency. In such systems, the Host/PCI-X bridge is designed to gather larger packets of split completion data from the main memory before sending these packets to the PCI-X device. For instance, the Host/PCI-X bridge can gather an entire first packet of 512 bytes from the main memory and send the first packet to the PCI-X device. When the Host/PCI-X bridge approaches the last byte of the first packet of 512 bytes, if Host/PCI-X bridge has not gathered an entire second packet of 512 bytes of split completion data from the main memory, the Host/PCI-X bridge stops after the last byte of the first packet. When the Host/PCI-X bridge has received the entire second packet of 512 bytes, the Host/PCI-X bridge sends the second packet of 512 bytes to the PCI-X device via the PCI-X bus 0, and so on. As a result, for the same amount of split completion data, if the packet size of 512 bytes/packet is used instead of 128 bytes/packet, the number of packets is reduced and so is the time during which the PCI-X bus 0 is idle. As a result, using a packet size of 512 bytes/packet likely reduces the time during which the PCI-X bus 0 is idle, compared with the case in which the packet size of 128 bytes/packet is used. Therefore, the systems using larger packets are more efficient. However, latency is worse because the first byte of the split completion data from the main memory is not sent to the PCI-X device by the Host/PCI-X bridge until the entire packet of 512 bytes is gathered by the Host/PCI-X bridge.
As a result, a conventional Host/PCI-X bridge that performs well in a system where efficiency is the main concern will perform poorly in another system where low latency is the main concern. Conversely, a conventional Host/PCI-X bridge that performs well in a system where low latency is the main concern will perform poorly in another system where efficiency is the main concern.
Accordingly, there is a need for an apparatus and method in which a Host/PCI-X bridge is adaptable to perform well in both a system where efficiency is the main concern and a system where low latency is the main concern.